Programming method for non-volatile memory device

ABSTRACT

Provided is a method of programming a non-volatile memory device. The method includes applying a first programming pulse to a corresponding wordline of the non-volatile memory device, applying a second programming pulse to the wordline, wherein a voltage of the second programming pulse is different from that of the first programming pulse, and applying voltages to each bitline connected to the wordline, the voltages applied to each of the bitlines are different from each other according to a plurality of bit values to be programmed to corresponding memory cells in response to the first programming pulse or the second programming pulse.

CROSS-REFERENCE TO RELATED PATENT APPLICATION

This application claims the benefit of Korean Patent Application No.10-2008-0017409 filed on Feb. 26, 2008, the subject matter of which ishereby incorporated entirety by reference.

BACKGROUND

The present invention relates to a method of programming a non-volatilememory device. More particularly, the invention relates to a method ofprogramming a non-volatile memory device which requires less time forprogramming and is capable of reducing coupling effect due to aprogramming sequence and/or cell distribution.

Non-volatile memory devices are electrically programmable and erasableand are able to retain stored data when supplied power is interrupted.Flash memory is one type of non-volatile memory and uses an electricalcharge to store data. Each of the memory cells forming a flash memorydevice includes a control gate, a charge storage layer, and a celltransistor having a source and a drain. The flash memory device changesthe data value stored by a memory cell by controlling the quantity ofcharge accumulated on the charge storage layer of the memory cell.

The cell transistor of the flash memory device controls the quantity ofcharge stored on the charge storage layer using the so-called F-Ntunneling phenomenon. An erase operation may be performed in relation toa cell transistor by applying a ground voltage to the control gate andby applying a voltage higher than a constituent power supply voltage tothe semiconductor substrate (or bulk). Under these erase biasconditions, a strong electric field is formed between the charge storagelayer and the semiconductor bulk due to a large difference in theelectrical resistances of same. As a result, charge accumulated on thecharge storage layer is discharged by F-N tunneling, and the criticalvoltage of the erased cell transistor decreases.

A programming operation may be performed in relation to the celltransistor by applying a voltage higher than the power supply voltage tothe control gate and applying a ground voltage to the drain, as well asthe semiconductor bulk. Under these programming bias conditions, chargeaccumulates on the charge storage layer due to F-N tunneling, and thecritical voltage of the cell transistor increases.

Hence, a memory cell state in which charge is relatively absent from thecharge storage layer and the corresponding critical voltage of the celltransistor is negative is conventionally referred to as an erased state.Further, a memory cell state in which charge accumulates on the chargestorage layer and the corresponding critical voltage of the celltransistor is greater than zero is referred to as a programmed state.

SUMMARY

Embodiments of the invention provide a programming method for anon-volatile device which is capable of reducing coupling effectscommonly associated with a programming sequence and/or celldistribution.

In one embodiment, the invention provides a programming method for amulti-level cell non-volatile memory device. The method includes;applying a first programming pulse to a wordline of the non-volatilememory device, applying a second programming pulse to the wordline,wherein a voltage level of the second programming pulse is differentfrom that of the first programming pulse, and applying bitline voltagesto respective bitlines associated with the wordline, wherein the bitlinevoltages vary in accordance with a plurality of data bit values to beprogrammed to a plurality of memory cells associated with the word lineand bitlines and in response to either the first programming pulse orthe second programming pulse.

In another embodiment, the invention provides a method of programming anon-volatile memory device, the method comprising; performing aprogramming operation during which at least one programming pulse thatvaries in relation to a plurality of 1^(st) through M^(th) data bitvalues to be programmed to a plurality of memory cells connected to awordline is applied to the wordline, and thereafter performing averifying operation, wherein execution timing of the verifying operationvaries in relation to the plurality 1^(st) through M^(th) data bitvalues.

In another embodiment, the invention provides a method of programming anon-volatile memory device, the method comprising; applying firstthrough N^(th), where is a natural integer greater than 1, programmingpulses to a word line, wherein respective voltage levels for the firstthrough N^(th) programming pulses are different, and applying bitlinevoltages to respective bitlines associated with the wordline, whereinthe bitline voltages vary in accordance with a plurality of data bitvalues to be programmed to a plurality of memory cells associated withthe word line and bitlines and in response to either the firstprogramming pulse or the second programming pulse.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1A is a diagram showing an example of programming one bit of datato a non-volatile memory device using two voltage distributions;

FIG. 1B is a diagram showing an example of programming two bits of datato the non-volatile memory device of FIG. 1A;

FIG. 1C is a diagram showing another example of programming two bits ofdata to the non-volatile memory cell using four voltage distributions;

FIG. 2A is a diagram showing an example of programming one bit of datausing two voltage distributions;

FIG. 2B is a diagram showing an example of programming two bits of datausing four voltage distributions;

FIG. 2C is a diagram showing another example of programming two bits ofdata using four voltage distributions;

FIGS. 3A and 3B are diagrams showing that voltage distributions ofmemory cells already programmed are shifted due to capacitive couplingsbetween adjacent wordlines or adjacent bitlines;

FIGS. 4A through 5B respectively are circuit diagrams showingnon-volatile memory devices in which memory cells connected to bitlinesadjacent to each other are simultaneously programmed;

FIGS. 6A through 6C are diagrams showing a coupling effect due to aprogramming sequence for a non-volatile memory device;

FIGS. 7A through 7C are diagrams showing a coupling effect due to a celldistribution in a non-volatile memory device;

FIG. 8 is a diagram showing a method of programming a non-volatilememory device that prevents the coupling effect due to a programmingsequence according to an embodiment of the invention;

FIG. 9 is a graph of voltages applied to bitlines during the programmingoperation illustrated in FIG. 8;

FIG. 10 is a diagram further illustrating the term “Vd” used in theembodiment of FIG. 9;

FIGS. 11 through 13 are diagrams showing a method of programming a threebit multi-level cell non-volatile memory device that prevents thecoupling effect due to a programming sequence according to an embodimentof the invention;

FIG. 14 is a diagram showing a plurality of programming operationssimultaneously performed according to the method of FIG. 8;

FIG. 15 is a diagram showing a method of programming a non-volatilememory device that prevents the coupling effect due to a celldistribution according to an embodiment of the invention;

FIG. 16 is a diagram showing a verifying voltage applied to a bitlineduring the method of FIG. 15;

FIG. 17 is a data table version of voltage diagram shown in FIG. 16; and

FIG. 18 shows programmed states for a non-volatile memory deviceprogrammed according method embodiments of the invention.

DESCRIPTION OF EMBODIMENTS

Several embodiments of the invention will now be described withreference to the attached drawings. The invention may, however, bevariously embodied and should not be construed as being limited to onlythe illustrated embodiments. Rather, the embodiments are presented asexamples teaching the making and use of the invention. Throughout thedrawings and written description, like reference indicators are used todenote like or similar elements.

FIG. 1A is a diagram showing an example of programming one bit of datato a non-volatile memory cell using two voltage distributions. When thedata bit value to be programmed is ‘0’, the critical voltage of anon-volatile memory cell is changed to be greater than 0V. That is, thecritical voltage of the non-volatile memory cell is placed in a secondvoltage distribution (VTHD2). In contrast, when the data bit value to beprogrammed is ‘1’, the critical voltage of the non-volatile memory cellremains unchanged and less than 0V. This assumes that the non-volatilememory cell is initially in an erased state, or that the criticalvoltage of the non-volatile memory cell is in a first voltagedistribution (VTHD1).

FIG. 1B is a diagram showing an example of programming two bits of datato the non-volatile memory cell using four voltage distributions. Aftera first bit of data (e.g., a least significant bit, LSB, of data) hasbeen programmed to the two-bit memory cell using the process describedin relation to FIG. 1A, a second bit of data (e.g., a most significantbit, MSB, of data) must be programmed. Thus, where the value of thefirst data bit is ‘0’, the non-volatile memory cell will initially beplaced in the second voltage distribution (VTHD2). Subsequently, wherethe value of a second bit of data to be programmed is also ‘0’, thecritical voltage of the non-volatile memory cell is changed to the thirdvoltage distribution (VTHD3). (See, operation 2-2 in FIG. 1B). However,where the second bit of data to be programmed in ‘1’, the criticalvoltage of the non-volatile memory cell remains in the second voltagethreshold distribution (VTHD2).

In similar manner, where the value of the first data bit is ‘1’, thenon-volatile memory cell initially remains in the first voltagedistribution (VTHD1), assuming an initially erased state. Subsequently,where the value of a second bit of data to be programmed is also ‘0’,the critical voltage of the non-volatile memory cell is changed to thefourth voltage distribution (VTHD4). (See, operation 2-1 in FIG. 1B).However, where the second bit of data to be programmed in ‘1’, thecritical voltage of the non-volatile memory cell remains in the firstvoltage threshold distribution (VTHD1).

FIG. 1C is a diagram showing another example of programming two bits ofdata to the non-volatile memory cell using four voltage distributions.

In the example shown in FIG. 1B, the critical voltage of thenon-volatile memory cell potentially changes between the first voltagedistribution and the fourth voltage distribution or between the secondvoltage distribution and the third voltage distribution as when thesecond bit of data is programmed. In contrast, in the example shown inFIG. 1C, the critical voltage of the non-volatile memory cellpotentially changes between the first voltage distribution and the thirdvoltage distribution (see, operation 3-1) or between the second voltagedistribution and the fourth voltage distribution (see, operation 3-2)when the second bit of data is programmed.

FIG. 2A shows a memory cell CELLA to be programmed in relation tosurrounding memory cells in an array of memory cells of a non-volatilememory device defined by intersecting word lines (WL) and bit lines(BL). It is assumed that the memory cell CELLA is initially programmedto have a critical voltage in the first voltage distribution (VTHD1),but may be programmed to have a critical voltage in any one of thesecond voltage distribution (VTHD2), third voltage distribution (VTHD3),or fourth voltage distribution (VTHD4).

FIG. 2B further shows that a voltage distribution for the programmedmemory cell CELLA may be shifted due to capacitive coupling (e.g., oneor more of Cx, Cy, and Cxy) between adjacent wordlines and/or bitlineswhen neighbouring memory cells are programmed after memory cell CELLAhas been programmed. Under these conditions the critical voltage ofmemory cell CELLA, which is intended to be within the second voltagedistribution (VTHD2) may be undesirably altered (e.g., broadened beyondthe defined range of the second voltage distribution VTHD2). AlthoughFIG. 2B specifically shows a case wherein the critical voltage of memorycell CELLA is intended to be in the second voltage distribution (VTHD2),the voltage distribution broadening caused by capacitive coupling mayoccur when the critical voltage for memory cell CELLA is intended to bein the first voltage distribution (VTHD1), the third voltagedistribution (VTHD3), or the fourth voltage distribution (VTHD4). In anyone of these cases, a voltage distribution for the programmed memorycell CELLA may become shifted. Similarly, although FIG. 2B shows anexample of voltage distribution shifting for memory cell CELLA under theinfluence of neighbouring cell programming from a first voltagedistribution (VTHD11) to a third critical voltage distribution (VTHD3),such voltage distribution shifting may occur in relation to otherprogramming operations applied to one or more of the neighbouring cells.

FIG. 3A is a circuit diagram showing a portion of a memory cell array ina non-volatile memory device in which memory cells connected to oddbitlines and memory cells connected to even bitlines are programmedseparately. That is, memory cells connected to a first bitline and athird bitline and memory cells connected to a second bitline and afourth bitline are programmed separately. Numbers 1 through 13 shown inFIG. 3A indicate an exemplary programming sequence. When the memorycells connected to odd bitlines are programmed after the memory cellsconnected to even bitlines are programmed, a programming voltage forprogramming the memory cells connected to the odd bitlines may changecritical voltages of the memory cells connected to the even bitlines dueto capacitive couplings between bitlines.

For example, the upper diagram shown in FIG. 3B (related to a LSBprogramming step) shows a voltage distribution for memory cellsconnected to the even bitlines being shifted from a defined secondvoltage distribution (VTHD2) to an errant voltage distribution (VTHDX)due to the programming of the memory cells connected to the odd bitlineswhich occurs after the first bit of data has been programmed to thememory cells connected to the even bitlines. The lower diagram shown inFIG. 3B (related to the MSB programming step) shows the possibleill-effects of subsequent voltage distribution transitions from or tothe errant voltage distribution (VTHDX).

FIGS. 4A through 5B are respective circuit diagrams showing non-volatilememory devices in which memory cells connected to bitlines adjacent toeach other are programmed simultaneously.

The non-volatile memory devices shown in FIGS. 4A through 5B are able toprevent undesired changes in voltage distributions due to capacitivecouplings Cx, Cy, and Cxy by programming memory cells connected to theadjacent bitlines simultaneously. Thus, partial memory cell array shownin FIG. 4A includes memory cells connected to a single wordline that areprogrammed simultaneously. FIG. 4B is a circuit diagram further showinga portion of the memory cell array of FIG. 4A.

Number 0 through 6 shown in FIG. 4B indicate an exemplary programmingsequence. Referring to these numbers, after a first plurality of memorycells (memory cells marked with number 0) connected to a first wordline(WL<n>) are programmed simultaneously, a second plurality of memorycells (memory cells marked with number 1) connected to a second wordline(WL<n+1>) are programmed simultaneously, etc.

In the non-volatile memory device shown in FIG. 5A, the memory cells ina memory cell array are also programmed on a page basis (i.e., within apage group). FIG. 5B is a circuit diagram showing a portion of thememory cell array of FIG. 5A.

Numbers 0 through 12 shown in FIG. 5B indicate another exemplaryprogramming sequence. Referring to the numbers, after a first pluralityof memory cells (memory cells marked with number 0) included in evenpage groups and connected to a first wordline (WL<n>) are programmed, asecond plurality of memory cells (memory cells marked with number 1)included in odd page groups and connected to the first wordline (WL<n>)are programmed, etc.

At this point in the programming operation described in relation toFIGS. 5A and 5B, if read current is simultaneously applied throughadjacent bitlines to read data from the adjacent memory cells, sensingnoise may occur due to capacitive coupling between adjacent bitlines. Toprevent sensing noise, the bitlines are divided into odd bitlines (e.g.,BLo1 and Blo2) and even bitlines (e.g., Ble1 and Ble2) and the readoperation or verify operation may be performed separately for oddbitlines and even bitlines. However, capacitive coupling may still occurin the method due to the programming sequence and/or cell distributionof a non-volatile memory device as described in some additional detailsbelow.

FIGS. 6A through 6C are diagrams further illustrating capacitivecoupling effects that may arise due to a programming sequence for memorycells within a non-volatile memory device.

Referring to FIG. 6A, the non-volatile memory device is assumed to be amulti-level flash memory device having multi-bit memory cells (i.e.,two-bit) capable of storing data bit values of: 11, 01, 00, and 10 inrelation to corresponding voltage distributions. As explained inrelation to FIG. 3B, a first voltage distribution associated with aninitial erase state (i.e., data value 11) may transition to a secondvoltage distribution associated with the data value 01, and a referencecritical voltage distribution ‘x0’ may then be shifted to the thirdvoltage distribution associated with the data value 00 or the fourthvoltage distribution associated with the data value 10.

At this point, as shown in FIG. 6B, a first programming operation P1 isperformed in relation to a memory cell of the non-volatile memorydevice, such that the first voltage distribution 11 transitions to thesecond voltage distribution 01. Then, a second programming operation P2is performed, such that the voltage distribution x0 is shifted to eitherthe third critical voltage distribution 00, or a third programmingoperation P3 is performed, such that the voltage distribution x0 isshifted to the fourth voltage distribution 10. In other words, aprogramming sequence varies in accordance with the data value to beprogrammed.

As suggested by FIG. 6B, each one of the first through third programmingoperations may be implemented as an incremental step pulse programming(ISPP) operation applied to a corresponding wordline in the non-volatilememory device. However, as shown in FIG. 6C, when the third programmingoperation P3 is performed on an adjacent memory cell after the firstprogramming operation P1 is performed, the second voltage distribution01 may be shifted by a value ΔVth. Thus, the non-volatile memory cellhas an errant voltage distribution (Err). In other words, although thefirst programming operation P1 is accomplished at a time t1 in the graphof FIG. 6C, the non-volatile memory cell may have a voltage distributiondifferent from the expected voltage distribution due to a capacitivecoupling effects because the third programming operation P3 issubsequently performed on adjacent memory cells at time t2.

FIGS. 7A through 7C are diagrams further showing capacitive couplingeffects due to cell distribution in a non-volatile memory device.Referring to FIG. 7A, a non-volatile memory device may form a voltagedistribution ‘b’ by shifting a voltage distribution ‘a’, as suggested bythe non-volatile memory device described in relation to FIG. 6A. At thispoint, memory cells may either be fast programmed or slow programmedaccording to the cell distribution of the non-volatile memory device.Therefore, when memory cells having the voltage distribution ‘a’ areprogrammed to have the voltage distribution ‘b’, programming time—whichis the time required to obtain the desired threshold voltagecorresponding to an intended data state—will vary according to theprogramming characteristics of the memory cells, as shown in FIG. 7B.

This difference in programming time causes a problem, as shown in FIG.7C. Although fast memory cells (FC) are completely programmed by timet1, slow memory cells (SC) require additional time to be completelyprogrammed when the voltage distribution ‘a’ is being shifted to thevoltage distribution ‘b’. Since programming voltages are continuouslyapplied to the fast memory cells (FC) until time t2—which is the pointin time when the slow memory cells (SC) are completely programmed—acoupling effect ΔVcell may occur. Thus, the critical voltagedistribution ‘b’ may be shifted by ΔVth so that the memory cells mayhave an errant voltage distribution (Err).

Hereinafter, methods of programming a non-volatile memory deviceaccording to certain embodiments of the invention will be described.These embodiments provide methods that prevent capacitive couplingeffects due to programming sequence and/or cell distribution.

FIG. 8 is a diagram showing a method of programming a non-volatilememory device that is capable of preventing capacitive coupling effectsdue to a programming sequence according to an embodiment of theinvention.

Referring to FIG. 8, the method of programming a non-volatile memorydevice applies a first programming pulse (PPLS1) to a correspondingwordline of the non-volatile memory device and applies a secondprogramming pulse (PPLS2), which has a voltage level different from thatof the first programming pulse (PPLS1), to the wordline.

In this case, the non-volatile memory device of FIG. 8 may be amulti-level cell flash memory device. For convenience of explanation, adescription specifically regarding to a 2-bit multi-level cell flashmemory device will be given hereinafter. A detailed descriptionregarding to multi-level cell flash memory devices having three or morebits will be described thereafter. Also, the method may be applied to asingle-level cell memory device.

Referring to FIG. 8, either the first programming pulse (PPLS1) or thesecond programming pulse (PPLS2) is a programming pulse corresponding toa plurality of bit values. For example, if the non-volatile memorydevice is a 2-bit multi-level cell flash memory device, the firstprogramming pulse (PPLS1) may be a programming pulse corresponding tothe second bit value 01 shown in FIG. 6A, and the second programmingpulse (PPLS2) may be a programming pulse corresponding to the fourth andthird bit values 10 and 00 shown in FIG. 6A.

In other words, the second programming operation P2 and the thirdprogramming operation P3, respectively corresponding to the fourth andthird bit values 10 and 00, may be performed simultaneously by applyingthe second programming pulse (PPLS2) of FIG. 8. Accordingly, as shown inFIG. 9, a plurality of voltages applied to each of the bitlines may bedifferent from each other according to the corresponding bit values forthe second programming pulse (PPLS2), such so as to perform programmingoperations for a plurality of bit values simultaneously according to theillustrated embodiment.

FIG. 9 is a graph of voltages applied to bitlines during the programmingoperation of FIG. 8.

Referring collectively to FIGS. 8 and 9, the voltages that are differentfrom each other according to bit values to be programmed to memory cellsmay be applied to each of the bitlines connected to wordlines to which aprogramming pulse regarding to a plurality of states is applied.

For example, like the embodiment shown in FIG. 8, when a programmingoperation associated with the fourth and third bit values 10 and 00 areperformed simultaneously by the second programming pulse (PPLS2),bitline voltages for the fourth and third bit values 10 and 00 may bedifferent from each other. Specifically, as shown in FIG. 9, when thebit value to be programmed to the memory cells is 00 and the bitlinevoltage is 0V, the bitline voltage when the bit value to be programmedto the memory cells is 10 may have a value Vd, wherein Vd is a voltagedifference between a median value of a voltage distribution in the casewhere a bit value of 10 is to be programmed (e.g., a third data state)and a median value of a voltage distribution in the case where a bitvalue of 00 is to be programmed (e.g., a fourth data state).

As shown in FIG. 10, when the median value of the voltage distributionfor the third data state is 2.4V, the median value of the voltagedistribution for the fourth data state is programmed is 3.8V. Thus, thevoltage difference Vd is 1.4V.

However, when the bit value to be programmed is 01, the bitlines do notreceive the second programming pulse (PPLS2), and an inhibit voltage Vddmay be applied to the bitlines not programmed by the second programmingpulse (PPLS2) the corresponding bitlines so as to deactivate thebitlines. Likewise, for a section ‘d2’ of the programming sequence shownin FIG. 9, including a narrower section ‘d1’ in which the firstprogramming pulse (PPLS1) is activated, the bitlines may be deactivatedby applying the inhibit voltage Vdd to the bitlines when the bit valuesto be programmed are 01 and 00.

Referring back to FIG. 8, the first programming pulse (PPLS1) and thesecond programming pulse (PPLS2) may be successively applied. At thispoint, a time interval between an application of the first programmingpulse (PPLS1) and an application of the second programming pulse (PPLS2)may be small enough not to cause the coupling effect due to theprogramming sequence as shown in FIGS. 6A through 6C.

Although FIGS. 8 through 10 show that an exemplary method of programminga non-volatile memory device according to an embodiment of the inventionincludes two programming pulses and one of the programming pulsesperforms programming operations corresponding to two bit valuessimultaneously, the present invention is not limited thereto. However,the voltage difference Vd related to cases in which the bit values to beprogrammed to a multi-level cell flash memory device (i.e. 00, 01, 10,and 11) is merely 1.4V as shown in FIG. 10, and thus it may be difficultto secure sufficient margin when the bitline voltages are setdifferently for each of the bit values within a range between 0V andVdd.

If sufficient margin may be obtained, more than two bit values may beprogrammed by a single programming pulse. Thus, the present inventionsubsumes embodiments capable of programming with a single programmingpulse.

Although FIGS. 8 through 10 show a method programming two bits to amulti-level cell flash memory device, the present invention is notlimited thereto. In other words, the method of the present invention maybe applied to multi-level cell flash memory devices having three or morebits.

FIGS. 11 through 13 are diagrams showing a method of programming threebits to a multi-level cell non-volatile memory device which is capableof preventing the capacitive coupling effects due to programmingsequence according to another embodiment of the invention.

Referring to FIGS. 11 through 13, the method of programming the threebits multi-level flash memory device may program eight memory cellstates associated with the three bits of data to a multi-level flashmemory device in response to three program pulses such that theresistances of the programmed memory cells change. At this point,critical voltage distributions for the programmed memory cells are shownin FIG. 13, numbered from P0 through P7.

More particularly, a first programming pulse (PPLS1) is applied to acorresponding wordline of the non-volatile memory device, a secondprogramming pulse (PPLS2) having a different voltage from that of thefirst programming pulse (PPLS1) is applied to the wordline, and a thirdprogramming pulse (PPLS3) having a different voltage from those of thefirst programming pulse (PPLS1) and the second programming pulse (PPLS2)is applied to the wordline. In like manner to the method of programmingthe two bits multi-level cell flash memory device, the first throughthird programming pulse (PPLS1 through PPLS3) can be activatedsuccessively.

Thus, the first programming operation P1 may be performed in response tothe first programming pulse (PPLS1), the second programming operation P2may be performed in response to the second programming pulse (PPLS2),and the third programming operation P3 may be performed in response tothe third programming pulse (PPLS3).

At this point, programming operations simultaneously performed by asingle programming pulse can program differently by applying differentbitline voltages. For example, when the second and fourth programmingoperations P2 and P4 are simultaneously performed by the secondprogramming pulse (PPLS2), bitline voltages different from each other,such as 0V, V1, and V2, may be applied to bitlines connected to memorycells corresponding to each of the second and fourth programmingoperations P2 and P4.

Also, the inhibit voltage Vdd may be applied to bitlines of memory cellscorresponding to second through seventh programming operations P2through P7 deactivated at a section in which the first programming pulse(PPLS1) is activated. The inhibit voltage Vdd may be applied to bitlinesof memory cells corresponding to the first programming operation P1 andthe fifth through seventh programming operation P5 through P7 which arenot activated by the second programming pulse (PPLS2). Likewise, theinhibit voltage Vdd may be applied to bitlines of memory cellscorresponding to first through fourth programming operations P1 throughP4 which are deactivated in a section in which the third programmingpulse (PPLS3) is activated.

Accordingly, a coupling effect due to a programming sequence can beprevented in multi-level cell flash memory devices having three or morebits.

Referring back to FIG. 8, a verifying operation verifying whether theprogramming operations are accurately performed by the first programmingpulse (PPLS1) and the second programming pulse (PPLS2) may be performed.At this point, the verifying operations regarding to different bitvalues can be separately performed whereas the programming operationsregarding to different bit values are performed simultaneously by thefirst programming pulse (PPLS1) and the second programming pulse(PPLS2), in the methods of programming according to embodiments of thepresent invention.

For example, if the method of programming according to the presentinvention employs an incremental step pulse programming (ISPP), FIG. 8shows a method of programming according to an embodiment of the presentinvention, in which three verification pulses VPLS, which indicateverifying operations regarding to the bit values 01, 11, and 10 shown inFIG. 6A, are activated between successive applications of the pair ofthe first programming pulse (PPLS1) and the second programming pulse(PPLS2).

At this point, verifying voltages applied to bitlines corresponding tobit values can have different magnitudes. However, the present inventionis not limited thereto, and a plurality of bit values can be verified ina single verifying operation.

Accordingly, in the methods of programming a non-volatile memory deviceaccording to embodiments of the invention, the first through thirdprogramming operations P1 through P3 regarding to a plurality of bitvalues are completed simultaneously or substantially simultaneously asshown in FIG. 14. Thus, any capacitive coupling effect influencing theprogrammed memory cells may be prevented, as shown in FIG. 6C.

FIG. 15 is a diagram showing a method of programming a non-volatilememory device according to an embodiment of the invention which hiscapable of preventing the capacitive coupling effects due to a celldistribution.

Referring to FIG. 15, the method of programming the non-volatile memorydevice according to the illustrated embodiment applies a programmingpulse regarding to a plurality of bit values 00, 01, and 10, but averification time of the programmed bit values are different from eachother. The verification time for each of the programmed bit values mayinvolve applying a different number of verifying voltages tocorresponding bitlines of the non-volatile memory device. At this point,voltages applied to the corresponding bitlines by the method ofprogramming shown in FIG. 15 may be different each time of application.For example, FIG. 15 shows that a verification regarding to the bitvalue 01 is performed by three different voltages Vvrf-1 through Vvrf-3,a verification regarding to the bit value 00 is performed by twodifferent voltages Vvrf-1 and Vvrf-2, and a verification regarding tothe bit value 10 is performed by a voltage Vvrf-1.

The voltage levels of the verifying voltages Vvrf-1 through Vvrf-3 maybe the same as what is shown in FIG. 16. FIG. 17 shows the magnitudes ofbitline voltages by comparing the magnitudes of the threshold voltagesVth and the verifying voltages Vvrf-1 through Vvrf-3 of a memory cell,regarding to the bit values.

Although FIGS. 15 through 17 are referred to describe the methods in atwo bits multi-level cell flash memory device, the present invention isnot limited thereto. Accordingly, the capacitive coupling effects due toa cell distribution may be reduced by having verification times thatdiffer according to bit values, in a method of programming according toan embodiment of the invention.

FIG. 18 shows programmed states for a non-volatile memory deviceprogrammed according to a method embodiment of the present invention.Referring to FIG. 18, programming operations P1 through P3 and/orprogramming operation according to cell distributions FC, TC, and SC arerespectively accomplished at time points t1 though t3, that is, almostsimultaneously. Therefore, a random change of a critical voltagedistribution due to the capacitive coupling effects due to programmingsequence and/or cell distribution shown in FIGS. 6C and 7C may beprevented.

While the present invention has been particularly shown and describedwith reference to exemplary embodiments thereof, it will be understoodby one of ordinary skill in the art that various changes in form anddetails may be made therein without departing from the scope of thepresent invention as defined by the following claims.

What is claimed is:
 1. A method of programming memory cells of amulti-level cell non-volatile memory to one of a plurality of datavalues, the method comprising: applying a first programming pulse to awordline of the non-volatile memory device and a first bitline voltageto at least one first bitline associated with the wordline correspondingto a first data value among a plurality of data values; applying asecond programming pulse to the wordline, a second bitline voltage to atleast one second bitline associated with the wordline corresponding to asecond data value among the plurality of data values, and a thirdbitline voltage to at least one third bitline associated with thewordline corresponding to a third data value among the plurality of datavalues, wherein a voltage level of the second programming pulse isdifferent from a level of the first programming pulse, the secondbitline voltage is different from the third bitline voltage if thesecond data value and third data value are different, the second bitlinevoltage is applied to the at least one second bitline and the thirdbitline voltage is applied to the at least one third bitlinesimultaneously, and a time interval required to apply both the firstprogramming pulse and the second programming pulse to the wordline issufficiently small to preclude substantial capacitive coupling betweenphysically proximate memory cells in the nonvolatile memory device. 2.The method of claim 1, wherein the second programming pulse is appliedto the wordline after the first programming pulse.
 3. The method ofclaim 2, further comprising: after applying the second programmingpulse, applying at least one of a sequence of verifying voltages to therespective bitlines, wherein a level of the at least one of the sequenceof verifying voltages varies in accordance with the data value to beprogrammed to the memory cell.
 4. The method of claim 3, whereinrespective levels of the verifying voltages in the sequence of verifyingvoltages sequentially increase, as applied during the verifyingoperation.
 5. The method of claim 3, wherein each one of the respectivelevels of the verifying voltages in the sequence of verifying voltagesis_less than levels of the first programming pulse and the secondprogramming pulse.
 6. The method of claim 3, wherein the method ofprogramming the multi-level cell non-volatile memory device is aniterative method comprising multiple programming loops, wherein eachprogramming loop comprises: applying the first programming pulse to thewordline and the first bitline voltage to the at least one firstbitline, and then applying the second programming pulse to the wordlineand the second bitline voltage to the at least one second bitline andthe third bitline voltage to the at least one third bitline voltage, andthen applying the at least one of the sequence of verifying voltages tothe bitline.
 7. The method of claim 6, wherein the level of the firstprogramming pulse and the level of the second programming pulserespectively increase with each successive iteration of the programmingloop.
 8. The method of claim 1, wherein the level of the firstprogramming pulse is less than the level of the second programmingpulse.
 9. A method of programming a non-volatile memory devicecomprising a first memory cell connected to a wordline and a firstbitline and a second memory cell connected to the wordline and a secondbitline, wherein the first memory cell and second memory cell aremulti-level non-volatile memory cells capable of being programmed to1^(st) through M^(th) data values, the method comprising: performing aprogramming operation during which the first memory cell is programmedto an i^(th) data value among the 1^(st) through M^(th) data valuesusing a first programming pulse applied to the wordline, and the secondmemory cell is programmed to a j^(th) data value among the 1^(st)through M^(th) data values using a second programming pulse differentfrom the first programming pulse and applied to the wordline, theprogramming operation comprising: simultaneously applying a firstbitline voltage having a first level and corresponding to the i^(th)data value to the first bitline, and a second bitline voltage having asecond level different from the first level and corresponding to thej^(th) data value to the second bitline; and performing a verifyingoperation on the first memory cell and second memory cell, whereinexecution timing for the verifying operation varies in relation to the1^(st) through M^(th) data values, wherein a time interval required toapply both the first programming pulse and the second programming pulseto the wordline is sufficiently small to preclude substantial capacitivecoupling between either the first memory cell and the second memory andat least one other memory cell physically proximate to the at least oneof the first memory cell and the second memory cell.
 10. The method ofclaim 9, wherein the verifying operation comprises: applying at leastone of a sequence of verifying voltages to the first and secondbitlines, wherein respective levels of the sequence of verifyingvoltages vary in accordance with a corresponding one of the 1^(st)through M^(th) data values.
 11. The method of claim 9, wherein theprogramming operation programs the i^(th) data value before programmingthe j^(th) data value, and the verifying operation comprises applying upto a first number of verifying voltages to verify the programming of thei^(th) data value and applying up to a second number of verifyingvoltages to verify the programming of the j^(th) data value, wherein thefirst number is greater than the second number.
 12. The method of claim11, wherein applying up to the first number of verifying voltagesrequires up to a first execution time, and applying up to the secondnumber of verifying voltages requires up to a second execution time,wherein the first execution time is greater than the second executiontime.
 13. An iterative method of programming memory cells of amulti-level cell non-volatile memory to one of a plurality of datavalues, the iterative method comprising multiple programming loops,wherein each programming loop comprises: applying a first programmingpulse to a wordline of the non-volatile memory device, and applying afirst bitline voltage corresponding to a first data value among aplurality of data values to a first bitline; applying a secondprogramming pulse having a level different from a level of the firstprogramming pulse to the wordline after applying the first programmingpulse to the wordline, and applying a second bitline voltagecorresponding to a second data value among the plurality of data valuesto a second bitline, and applying a third bitline voltage correspondingto a third data value among the plurality of data values to a thirdbitline, wherein the second bitline voltage is applied to the secondbitline and the third bitline voltage is applied to the third bitlinesimultaneously, wherein the second bitline voltage is different from thethird bitline voltage if the second data value and third data value aredifferent; and after applying the second programming pulse, applying atleast one of a sequence of verifying voltages to the first bitline andthe second bitline, wherein a level of the at least one of the sequenceof verifying voltages varies in accordance with a data value beingprogrammed to the memory cell.
 14. The method of claim 13, wherein thelevel of the first programming pulse and the level of the secondprogramming pulse respectively increase with each successive iterationof the programming loop.